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Integral Solutions

Verification Engineer

Integral Solutions Show all offers
Warszawa
Expires Nov 29, 2026
3 days ago

In short

Verification Engineer in Warsaw. Develop UVM testbenches, verification plans, and coverage models. Requires B.

Sc./M.

Sc. in EE/CS, ~5 years of ASIC/SoC verification experience, SystemVerilog, UVM, bus protocols, EDA tools, and scripting. Benefits include medical care, sports subsidies, and language classes.

Keywords

SystemVerilog UVM ASIC verification SoC verification AXI Python Bash EDA tools RTL simulation gate-level simulation

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We collected this offer from another job board and only hold its basics.
Published 2026-10-30
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