Asic Back-End / Physical Design Engineer multiple

Resquant Zobacz wszystkie oferty

22000 - 29000 PLN / miesiąc

Praca zdalna

2 miesiące temu

W skrócie

ASIC Back-End / Physical Design Engineer (multiple) at Resquant. Responsibilities include full physical implementation flow, timing closure, power planning, and low-power architectures for quantum-resistant cryptographic processors. Salary: 22,000-29,000 PLN gross/month. Full-time, hybrid/remote.

Słowa kluczowe

ASIC Physical Design FPGA Chip Security Cryptography Semiconductor STA Power Planning Low-Power Design GF 22FDX

Skrót przygotowany przez AI na podstawie treści ogłoszenia.

ASIC Back-End / Physical Design Engineer (multiple)

Resquant is a rapidly growing deep-tech startup focused on next-generation chip security and quantum-resistant cryptography solutions for dual-use and high-security applications. We develop advanced hardware security technologies designed to address emerging threats in post-quantum computing environments, working at the intersection of cryptography, semiconductor engineering, and secure system architecture.

We are building a team of highly skilled engineers passionate about cutting-edge FPGA and ASIC development, secure hardware design, and innovative defense-grade technologies.

Position: ASIC Back-End / Physical Design Engineer (multiple)

Compensation: 22,000–29,000 PLN gross/month

Employment type: Polish employment contract

Resquant is looking for highly skilled ASIC Back-End / Physical Design Engineers for various positions. This is a great opportunity to join a rapidly growing startup at an early stage, working on the latest trends in chip security and cryptography. The project targets the GlobalFoundries 22 nm FDX (22FDX) FD-SOI platform.

Main responsibilities:

Driving the full physical implementation flow — floorplanning, placement, clock tree synthesis (CTS), and routing — for quantum-resistant cryptographic processors.
Performing timing closure and static timing analysis (STA) signoff across multiple corners and modes (setup/hold).
Power planning and analysis, including IR-drop and electromigration (EM) checks.
Implementing low-power architectures: power domains, level shifters, isolation cells, and the body-bias distribution network required for Adaptive Body Bias (ABB) on GF 22FDX FD-SOI.
Handling synthesis-to-layout handoff, ECOs, and tapeout preparation in cooperation with the foundry (GlobalFoundries).
Participation in certification and technical documentation development.

What do we offer:

Full-time Senior and Mid-level positions
Salary range: 22,000–29,000 PLN gross/month, depending on experience and seniority.
Employment under an employment contract
Participation in projects aimed at providing a backbone for chip security for dual-use markets.
Flexible working hours.
Ability to work remotely (Hybrid/Full).
Equity options.
Broad technical ownership.
Innovation and cutting-edge projects.
Opportunity to attend closed events with military representatives.