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RESQUANT sp. z o.o.

FPGA Design Engineer

RESQUANT sp. z o.o. Show all offers
Łódź
Expires Oct 16, 2026
2 days ago

In short

FPGA Design Engineer in Łódź. Responsibilities include RTL design for crypto algorithms, micro-architecture definition, synthesis, and integration. Requires Bachelor's/Master's degree, 5-8+ years of FPGA experience, VHDL/Verilog/SystemVerilog proficiency, ASIC design knowledge, and timing analysis. Benefits: remote work, flexible hours.

Keywords

FPGA RTL Design VHDL Verilog SystemVerilog ASIC Design Timing Analysis Cryptography RISC-V

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Published 2026-09-16
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