Senior Logic Design Engineer (FPGA/ASIC)

Locations: Ukraine, Poland, Czech Republic, Romania, Slovakia, Spain

We are recruiting a Senior Logic Design Engineer to develop high-performance FPGA/ASIC digital logic for advanced quantum computing control and measurement technology.

This hands-on R& D role involves designing configurable, low-latency hardware and collaborating with architects, verification engineers and software specialists.

DCV.

CK.

JO.28.10.2026

Responsibilities

• Design and implement complex SystemVerilog RTL modules.
• Develop signal processing, waveform generation and real-time control logic.
• Contribute to architecture, microarchitecture and RTL integration.
• Perform synthesis, static timing analysis and optimization.
• Debug and verify RTL functionality with verification teams.
• Integrate digital IP and hardware-software interfaces.

Requirements

• 4+ years of professional FPGA/ASIC digital logic design experience.
• Strong hands-on SystemVerilog RTL development.
• Solid understanding of digital microarchitecture and synchronous design.
• Experience with synthesis, STA, timing optimization and CDC.
• Practical FPGA/ASIC implementation and RTL debugging experience.
• Confident English (B2+).

Advantages: AMD/Xilinx Versal, Vivado, Questa/VCS, DSP, high-speed interfaces, ASIC IP, Python/Tcl automation and hardware-software co-design.