Verification Engineer

Technologies we use

About the project

Your responsibilities

• Develop, maintain, and execute UVM-based verification environments, testbenches, scoreboards, and reusable VIPs.
• Define and implement comprehensive verification plans based on architecture and design specifications.
• Construct functional coverage models, analyze code coverage, and drive coverage closure.
• Write SystemVerilog for protocol checking and interface verification.
• Perform root-cause debugging of complex hardware issues at both RTL and gate-level simulations.
• Collaborate with design and architecture teams to resolve bugs and refine feature specifications.
• Automate regression suites, test execution, and result tracking using scripting tools.

Our requirements

• Education: B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field.
• Experience: ~5 years of proven experience in ASIC/SoC digital functional verification.
• Core Expertise:
• Advanced proficiency in SystemVerilog and UVM.
• Strong hands-on experience building UVM testbenches from scratch or extending existing frameworks.
• Solid understanding of standard bus protocols (e.g., AXI, AHB, APB, PCIe, or Ethernet).
• Hands-on experience with industry-standard EDA simulation and debug tools (Cadence Xcelium, Synopsys VCS, Siemens Questa, DVE/Verdi).
• Proficiency in scripting languages (Python, Perl, or Bash) for verification automation.
• Soft Skills: Excellent problem-solving abilities, strong communication skills, and a collaborative team mindset.

Benefits