Expert Logic Design Engineer (FPGA/ASIC)

DCV Technologies Усі вакансії

Poland Remote

Діє до 13 лис 2026

4 дні тому

Коротко

Expert Logic Design Engineer (FPGA/ASIC) for quantum computing R&D in Poland. Responsibilities include digital architecture, RTL implementation, and optimization. Requires 6+ years FPGA/ASIC experience and SystemVerilog RTL design. Offers remote work.

Ключові слова

FPGA ASIC SystemVerilog RTL design digital architecture microarchitecture STA timing closure CDC quantum computing

Стислий виклад підготував ШІ на основі тексту оголошення.

Expert Logic Design Engineer (FPGA/ASIC)

Locations: Ukraine, Poland, Czech Republic, Romania, Slovakia, Spain

DCV.

CK.

JO.28.10.2026

Send CV to [email protected]

We are recruiting an Expert Logic Design Engineer for an advanced R& D project developing FPGA- and ASIC-based control and measurement systems used in quantum computing.

You will take technical ownership of complex, high-performance digital subsystems, working on next-generation hardware where deterministic timing, low latency and design quality are critical.

Responsibilities

Lead digital architecture, microarchitecture and SystemVerilog RTL implementation.
Design configurable, ultra-low-latency digital logic and reusable IP.
Drive design from specification through synthesis, timing closure and integration.
Optimize clocking, CDC, resource utilization, power and critical paths.
Collaborate with verification, software and hardware engineering teams.
Guide technical decisions, design reviews and engineering improvements.

Requirements

6+ years of professional FPGA/ASIC digital logic design experience.
Expert hands-on SystemVerilog RTL design.
Proven ownership of complex digital IP from specification to implementation.
Advanced knowledge of synthesis, STA, timing closure and CDC.
Strong digital architecture and microarchitecture experience.
Technical leadership and confident English (B2+).

Advantages: AMD/Xilinx Versal, Vivado, ASIC development, DSP, waveform generation, AXI/PCIe/DDR, Questa/VCS, Python or Tcl, quantum computing or high-performance instrumentation.